This is only a little part of one our article published in IEEE journal.
|
DSP Core for Hardware Based CIL Machine |
|
Dmitry V. Ragozin, Maxim O. Shuralev, Maxim A. Sokolov, and Dmitry K. Mordivinov
Laboratory of Physical Fundamentals and Technology of Wireless Communication
Radiophycics Department
Nizhny Novgorod State University
Gagarina avenue 23 block 1, Nizhny Novgorod, 603000, Russian Federation
E-Mail: {ragozin,max,sim, psihei}@wl.unn.ru
|
Abstract— The paper presents a DSP core implementation for a prototype of the CIL hardware engine, which is targeted for .NET paradigm support on mobile devices. The features of a convergent DSP-CIL processor are considered in the paper. The architecture of the DSP kernel of the CIL processor – a 32-bit fixed-point core with 3-stage pipeline, which issues up to 5 operations per cycle – is considered here. To provide the DSP core verification a testing framework for performing automated core tests is developed, its test pattern generator is able to generate instruction sequences with variable distribution of different instruction classes. Finally, the results of DSP core implementation on Xilinx FPGA Virtex series are given.
Index Terms— computer architecture, digital signal processors, logic circuit testing, microprocessor testing.
I. INTRODUCTION
In the fall of 2004 Laboratory of Physical Fundamentals and Technologies of Wireless Communications, supported with Microsoft grant, started the implementation of a hardware-based CIL processor prototype. The goal of the CIL processor research and development activities is to propose a hardware CIL processor model, which can enable .NET technology for low-power and mobile devices. Regardless of the fact that desktop computers and handheld devices have .NET environment, mobile devices have to use much cheaper (in terms of hardware) resources for .NET environment, and it is a good idea to implement CIL support in hardware.
But, a stack-based virtual machine is not so effective for processing modern multimedia content. So, an attempt to create a CIL processor, which has reasonable performance in multimedia applications, looks challenging. By the course of our research we were developed a convergent solution, which includes a DSP core and two decoders, which can efficiently handle both DSP and CIL instruction sets.
In chapter 2 the foundations of our convergent CIL processor concept are described. In chapter 3 the high-level schematic of the CIL processor implementation is considered. In chapter 4 the DSP core implementation is considered. Chapter 5 is dedicated to test framework, which is aimed to verify the core with semi-random instruction sequences automatically.
II. convergent processor concept
As software concept .NET technology is very similar to Java technology. .NET software is intended for “safe” execution model “once written – executing on any platform” for software transmission over the Internet and safe execution over different hardware platforms. .NET is implied for converging different computational devices — .NET resources must be accessible for mobile phones, PDAs, different handhelds, desktop computers. But, .NET platform software utilizes so many resources, that its port to mobile devices, which have less resources than typical modern PDA (400Mhz XScale with 32 MB RAM), should be ineffective. An important problem here is amount of consumed electrical energy – true mobile devices should work much longer than 5-6 hours (like PDAs). Therefore, the implementation of a CIL engine “in hardware” is a very attractive idea, it allows, for example, to implement whole digital home concept using .NET technology.
Like a Java machine, .NET engine is based on abstract stack machine implementation. The stack machine is a very good formal approach to a virtual machine implementation, but a .NET stack-based interpreter can not be mapped easily (without the help of Jist-in-Time Compiler – JIT) on RISC-processor – an interpreter will execute CIL code ten times slower than a JIT-compiler does the native code.
So, a straightforward attempt for the CIL processor implementation should be the implementation of a typed stack machine, as the stack engine is probably the simplest processor implementation [1]. As the stack machine does not use direct register addressing, instruction decoding is very simple, and instruction execution cycle is very short, and there are no additional multiplexer switches for read and write ports as in RISC register file. Though the stack processor has limited ability for parallel execution, it has low complexity and low power consumption, as there is no large multiplexer schematic for the stack engine registers.
Another opportunity is the hardware emulation of CIL engine. E.g., , there are different approaches to Java processor implementation for mobile devices: a Java-oriented coprosessor, such as [2] or a technology, such as Jazelle [3], where two additional pipeline stages are integrated into the ARM core. These extra pipeline stages decode Java instructions so that they can be executed directly as usual ARM RISC instruction. Thus, the hardware CIL processor also can be implemented in such a way — on the top of some processor core.
Sure, the CIL processor can not be a competitor for desktop and PDA market, but end-user specialized devices, like Web-terminals, interactive TV-sets, digital home systems and other devices are a good target. The processor must handle multimedia Internet content (tasks like MPEG1/2/3 playback, MPEG4 and DVD video playback, Flash playing), consuming low energy. Therefore, we decided to implement a dual-decoder scheme, where a processor core can execute two instruction sets (CIL and DSP) as the native code.
____________________________________________________________________________________________________________
VI. Conclusion
If compared to competitive implementations, like software ARM-based .NET-CPU [9], the hardware CIL implementation has 30-50x speedup if a FPGA DSP core
(at 30-80 Mhz) is compared with software ARM-based implementation of .NET-CPU. Surely, it can not compete with .NET JIT on PC, but it is a good implementation for some mobile market segments. And, besides the speedup values, our research shows, that an efficient CIL processor implementation is possible on the top of DSP core, which is unusual for implementation of such kind of processor. It seems that depending on necessary target, an ARM core or another RISC core can be used as a basic core for the CIL hardware processor.
The DSP core can be used as a standalone core, and the developed verification system will be used for testing implementation of other DSP cores, which are developed in Wireless Laboratory of NNSU.
Acknowledgment
The authors are thankful to Aliaksei V. Chapyzhenka for gently advices and suggestions on DSP core architectures and to Alexey L. Umnov, Head of Wireless Laboratory in Nizhny Novgorod State University for supporting project activities in the Laboratory.
Dmitry V. Ragozin Was born is Chernigov, 1977. Engineer diploma in Computer Science from Chernigov branch of Kiev Politechnical Institute, Chernigov, Ukraine, 1999. Ph. D. in Computer Science from Institute of Software Systems of Ukrainian Academy of Science, Kiev, Ukraine (2003). Major field of study: compilers and compilation technologies.
He works for Intel Nizhny Novgorod Labs as Research Scientist and devotes his time to different educational and research activities in Nizhny Novgorod State University as assistant professor. He published more than a dozen of articles in different ex-USSR and foreign journals. His main research activities are: compiler and microprocessor technologies, parallel programming and sensor networks.
Maxim O. Shuralev Was born in Nizhny Novgorod, Russia, 1985. Bachelor of Science degree from Nizhny Novgorod State University (NNSU).
He is getting M.Sc. now at Radiophysics department of NNSU and is in stuff of Laboratory of physical basics and technologies of wireless communication of Radiophysical department, NNSU. He published about ten articles in Russian journals. His main research activities are: chip and programmable logic design, testing, wireless communications, electrodynamics.
Maxim A. Sokolov Was born in Nizhny Novgorod, Russia, 1984. Bachelor of Science degree from Nizhny Novgorod State University (NNSU) in 2005.
He is getting M.Sc. now at Radiophysics department of NNSU and is in stuff of Laboratory of physical basics and technologies of wireless communication of Radiophysical department, NNSU. His research interests are: wireless communications, error control coding, programmable logic design and testing.
Dmitry K. Mordvinov Was born in Nizhny Novgorod, Russia, 1984. Bachelor of Science degree from Nizhny Novgorod State University (NNSU) in 2005.
He is getting M.Sc. now at Radiophysics department of NNSU and is in stuff of Laboratory of physical basics and technologies of wireless communication of Radiophysical department, NNSU. His research interests are: wireless communications, programmable logic design and testing, electodynamics.